VTERB-DECO-XP-N1【PDF 17/20 页】IP CORE VITERBI DECODER XPGA

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Lattice Semiconductor

Viterbi Decoder User’s Guide

10. Double click on Place & Route Design . This will place and route the mapped design. If there are no errors in

this process, a green mark appears next to the Place & Route Design process (Figure 23).

11. Double click on Generate Timing Simulation Files . This generates the ?les for the optional back-end timing

simulation (project_name.v and project_name.sdf). If there are no errors in this process, a green mark appears

next to the Generate Timing Simulation process (Figure 23).

12. Double click on Generate Bitstream Data . This generates the bitstream ?le used to program the target device.

If there are no errors in this process, a green mark appears next to the Generate Bitstream Data process

(Figure 23).

ispLEVER Software Flow for ispXPGA Devices

The following steps illustrate ispLEVER software ?ow for XPGA devices:

1. Create a project directory.

2. Copy the synthesized design EDIF ?le and the Viterbi Decoder core netlist to the project directory.

3. Launch the ispLEVER software. Figure 18 shows the ispLEVER Project Navigator Window .

4. Select File > New Project and create or browse to the project directory. All the design ?les will be generated in

this directory. Figure 19 shows the New Project Creation Dialog Box . Type the project name and select EDIF

as a project type.

5. Double click on the device name in the Process Window of the Project Navigator and select the device.

Figure 20 shows the Device Selection Dialog Box .

6. Select Source > Import . The Import File Dialog Box as shown in Figure 21. Enter the EDIF ?lename and

click Open . The Import EDIF Dialog Box as shown in Figure 22. Select the EDIF vendor type and click OK .

The EDIF ?le will then be added to the project.

7. Double click on the Build Database . This will read the EDIF netlist and generate the design database. If there

are no errors in the process, you will see a green mark next to the Build Database process (Figure 24).

8. Double click on the Constraint Editor . You can enter the required preferences including the pin locking using

the Constraint Editor. You can also create ASCII constraint ?le using a text editor. For additional details on the

XPGA constraints, refer to ispLEVER online documentation.

9. Double click on the Pack & Place Design . This will pack and place the design into the physical elements. If

there are no errors in the process, you will see a green mark next to the Pack & Place Design process

10. Double click on the Route Design . This will route the pack and placed design. If there are no errors in the pro-

cess, you will see a green mark next to the Route Design process (Figure 24).

11. Double click on the Timing Analysis . This will execute static timing analyzer on the routed design. If there are

no errors in the process, you will see a green mark next to the Timing Analysis process (Figure 24).

12. Double click on the Generate Timing Simulation Files . This will generate the ?les ( project_name .vo and

project_name .sdf) for the back-end timing simulation. If there are no errors in the process, you will see a green

mark next to the Generate Timing Simulation process (Figure 24).

13. Double click on the Generate Bitstream Data . This will generate the bitstream ?le for programming. If there

are no errors in the process, you will see a green mark next to the Generate Bitstream Data process

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